1. Field of the Invention
The present invention relates generally to an arithmetic processor and more particularly to a high-speed leading one anticipator capable of anticipating the uppermost position of significant digits in the result of a floating point addition or subtraction. The leading one anticipator according to the present invention is particularly effective when non-significant digits are generated at upper-order digit positions upon addition or subtraction of two floating point data each having a mantissa part, an exponent part, and a sign part. The present invention also relates to a floating point addition/subtraction apparatus employing a leading one anticipator of the above-described type.
2. Description of the Prior Art
Conventionally, when a mantissa subtraction is performed with respect to two floating point data X and Y each having a mantissa part, an exponent part, and a sign part, a digit alignment, a mantissa addition or subtraction, and a normalization are performed in this order.
The digit alignment is initially discussed hereinafter with reference to FIG. 1 depicting a conventional floating point addition/subtraction apparatus.
Exponent parts (Xe, Ye) of two operands are inputted into a subtracter 405, a SHIFT-signal generator 404, and a selector 406. At the same time, mantissa parts (1.Xf or 0.Xf, 1.Yf or 0.Yf) of the two operands are inputted into a right/left shifter 401, which shifts the mantissa parts right or left by one digit. The subtracter 405 performs a subtraction with respect to the exponent values Xe and Ye to calculate an absolute value .vertline.Xe-Ye.vertline. and a sign value S(Xe-Ye). At the same time, the SHIFT-signal generator 404 detects whether or not the individual operands are normalized numbers with the use of respective exponent values Xe and Ye and generates control signals required for shifting respective mantissa values right or left by one digit with the use of respective sign values (Xs, Ys) and a subtraction signal SUB. This control is disclosed, for example in Japanese Patent Application No. 1-38687. Based on the control signals from the SHIFT-signal generator 404, the right/left shifter 401 shifts the two mantissa values right or left. Outputs from the right/left shifter 401 are inputted into a swapping circuit 402 in which they are swapped in accordance with the sign value S(Xe-Ye) outputted from the subtracter 405 so that the mantissa value of one operand having an exponent value not greater than that of the other operand may be inputted into a right barrel shifter 403 whereas the mantissa value of the latter having a greater exponent value may be inputted into an adder/subtracter 407. The right barrel shifter 403 shifts right the mantissa value inputted thereinto by the absolute value .vertline.Xe-Ye.vertline., which is indicative of the difference between the two exponent values and is outputted from the subtracter 405. The digit alignment is performed in this way.
The adder/subtracter 407 then performs an addition/subtraction processing and a rounding processing.
Subsequently, the normalization processing is discussed hereinafter.
When the result of a subtraction in which the exponent value Ye is subtracted from the exponent value Xe is "0", "1", or "-1", there is a possibility of a digit drop occurring in a mantissa part of the result of a subtraction with respect to the mantissa parts of the two operands. The digit drop is a phenomenon in which non-significant digits are generated at upper digit positions. A priority encoder (PE) 408 and a left barrel shifter 409 are required to normalize this mantissa value. An output from the adder/subtracter 407 is inputted to both the PE 408 and the left barrel shifter 409. Based on the output from the adder/subtracter 407, the PE 408 detects a left shift amount required for normalization, and based on the left shift amount detected by the PE 408, the left barrel shifter 409 normalizes the result of the mantissa subtraction.
As to the two exponent values Xe and Ye inputted into the selector 406, one exponent value which is not less than the other is selected in accordance with the sign value S(Xe-Ye). An output from the selector 406 is inputted into a subtracter 410, which subtracts the shift amount detected by the PE 408 therefrom to obtain an exponent value of the result of a floating point addition/subtraction.
In this way, in order to normalize the result of the mantissa subtraction, the conventional floating point addition/subtraction apparatus detects the number of upper non-significant digits contained in the result of the mantissa subtraction by the use of the PE 408 and performs a normalization based on the amount detected.
Accordingly, the mantissa subtraction, the detection of the shift amount required for normalization, and the normalization are consecutively performed, thereby retarding the floating point addition/subtraction speed.